Training schedule
The calendar below shows scheduled inter-company training sessions, including completed sessions retained in the history.
Periods without a displayed session do not necessarily indicate availability: they may be devoted to intra-company or bespoke training, expert consulting and technical support assignments, as well as the preparation and adaptation of training courses.
Monthly view
Browse scheduled sessions and the history of completed sessions. Dates shown in green remain available for requests.
May 2026
2 sessionsJune 2026
1 sessionAugust 2026
1 sessionSeptember 2026
3 sessionsOctober 2026
5 sessionsSessions and requests this month
VER_ARC - Designing with Versal™ Gen1 & Gen2 : Architecture, Tools and Methodology
Location: ONLINE | 3600 €
The standard deadline has passed: contact us until the day before the start.Next session: March 1, 2027VER_NOC - Designing with the Network On Chip of AMD Versal™
Location: ONLINE | 1200 €
Standard registration is available until D-7.W_VIVADO_AI - Using the AMD Ross™ Agentic AI Assistant for Vivado™ Design Suite
Location: ONLINE | 0 €
Standard registration is available until D-7.AIE_DSGN - Designing with Versal™ AI Engine (AI, AIE-ML, AIE-MLv2)
Location: ONLINE | 3600 €
Next session: April 12, 2027November 2026
4 sessionsSessions and requests this month
L_VV_UP - VHDL to Verilog and Verilog to VHDL
Location: ONLINE | 2200 €
Next session: January 7, 2027E_ZAHS - The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components
Location: ONLINE | 3600 €
Next session: March 15, 2027W_RYZENAI_CVML - Local Computer Vision with AMD Ryzen™ AI and CVML
Location: ONLINE | 0 €
Standard registration is available until D-7.F_VBASE - Designing FPGAs Using the Vivado™
Location: ONLINE | 3600 €
Standard registration is available until D-7.Next session: May 18, 2027December 2026
4 sessionsSessions and requests this month
F_VBASE - Designing FPGAs Using the Vivado™
Location: ONLINE | 3600 €
Standard registration is available until D-7.Next session: May 18, 2027F_STAXDC - Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™
Location: ONLINE | 3600 €
Next session: February 8, 2027L_VHDL - VHDL Logical Synthesis and Simulation for AMD FPGA design
Location: ONLINE | 4400 €
Next session: February 1, 2027W_USGEN2 - Introduction to the Spartan™ and Kintex™ UltraScale+™ Gen 2 Architecture
Location: ONLINE | 0 €
Standard registration is available until D-7.January 2027
1 session | 2 open weeksSessions and requests this month
L_VV_UP - VHDL to Verilog and Verilog to VHDL
Location: ONLINE | 2200 €
Standard registration is available until D-7.Week open for requests
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Week open for requests
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February 2027
2 sessions | 2 open weeksSessions and requests this month
L_VHDL - VHDL Logical Synthesis and Simulation for AMD FPGA design
Location: ONLINE | 4400 €
Standard registration is available until D-7.F_STAXDC - Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™
Location: ONLINE | 3600 €
Standard registration is available until D-7.Week open for requests
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Week open for requests
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March 2027
2 sessions | 3 open weeksSessions and requests this month
VER_ARC - Designing with Versal™ Gen1 & Gen2 : Architecture, Tools and Methodology
Location: ONLINE | 3600 €
Standard registration is available until D-7.E_ZAHS - The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components
Location: ONLINE | 3600 €
Standard registration is available until D-7.Week open for requests
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Week open for requests
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Week open for requests
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April 2027
1 session | 4 open weeksSessions and requests this month
AIE_DSGN - Designing with Versal™ AI Engine (AI, AIE-ML, AIE-MLv2)
Location: ONLINE | 3600 €
Standard registration is available until D-7.Week open for requests
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Week open for requests
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Week open for requests
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Week open for requests
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May 2027
2 sessions | 3 open weeksSessions and requests this month
D_HLS - High-Level Synthesis with the Vitis Unified IDE
Location: ONLINE | 3000 €
Standard registration is available until D-7.F_VBASE - Designing FPGAs Using the Vivado™
Location: ONLINE | 3600 €
Standard registration is available until D-7.Week open for requests
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Week open for requests
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Week open for requests
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June 2027
0 session | 3 open weeksSessions and requests this month
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July 2027
0 session | 3 open weeksSessions and requests this month
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Browse by topic
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Versal™ Gen1 & Gen2 Architecture, Tools and methodology
E_ZAHS The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components
Learn system architecture, hardware and software design of Zynq™-7000, Zynq™ MPSoC and Versal™ components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104.
VER_ARC Designing with Versal™ Gen1 & Gen2 : Architecture, Tools and Methodology
Understand the architecture of AMD Versal™ Gen1 and Gen2 devices and learn the methods needed to design, integrate, configure, simulate, and debug a heterogeneous system that leverages their key hardware and software resources.
Versal™ Gen1 & Gen2 AI Engines
AIE_DSGN Designing with Versal™ AI Engine (AI, AIE-ML, AIE-MLv2)
Acquire the knowledge and skills required to design, program, analyze, and optimize applications using AMD Versal™ AI Engines, by leveraging kernel-based and dataflow graph programming models as well as associated DSP libraries.
Versal™ Gen1 & Gen2 Connectivity
VER_NOC Designing with the Network On Chip of AMD Versal™
Learn how to use the NoC to efficiently move your data through Versal™ components.
VER_TRX Designing with Versal™ Serial Transceivers
Learn how to use Versal™ GTY and GTM serial transceivers
VER_PCIE Designing an Integrated PCI Express® System for Versal™
Identify and construct a PCI Express® system on Versal™
Embedded design for AMD SoCs
E_ZAHS The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components
Learn system architecture, hardware and software design of Zynq™-7000, Zynq™ MPSoC and Versal™ components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104.
Design with the Zynq™ UltraScale+ RFSoC
C_RFSOC Design with the Zynq™ UltraScale+ RFSoC
Learn to use the RF Data Converter blocks of the RFSoC.
Digital Signal Processing on FPGA
D_ESS Essential DSP implementation techniques for AMD FPGAs
Understand and effectively use the resources of AMD FPGAs for implementing digital signal processing algorithms.
FPGA Architectures and High-Speed Interfaces
F_SU Designing with the AMD UltraScale+™ Families (Spartan™ included)
Learn how to effectively use AMD UltraScale+™ architectural resources
C_TRX Designing with Serial Transceivers
Learn how to use serial transceivers in your UltraScale™, UltraScale+™ FPGA or Zynq™ UltraScale + MPSoC.
C_PCIE Designing an Integrated PCI Express System
Acquire the knowledge and skills required to design, configure, simulate, implement, and debug a PCI Express® interface on AMD FPGAs and SoCs, by mastering the PCIe protocol, associated IP solutions, and their integration into a system architecture.
Vivado™ & Vitis™ HLS
D_HLS High-Level Synthesis with the Vitis Unified IDE
Improve the productivity of components for Programmable Logic (FPGAs) using the Vitis™ HLS tool
F_VBASE Designing FPGAs Using the Vivado™
Designing an FPGA design, which includes creating a Vivado™ Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design.
F_STAXDC Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™
Understand XDC Timing constraints, Static timing analysis, good AMD FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite
F_DFX Designing with Dynamic Function eXchange (DFX) Using the Vivado™
Learn how to build et assembly reconfigurable partitions to configure partially et dynamically a AMD component
VHDL
L_VHDL VHDL Logical Synthesis and Simulation for AMD FPGA design
Acquire the knowledge and skills required to design, synthesize, implement, and simulate digital architectures in VHDL on AMD FPGAs, by mastering the main FPGA hardware resources, RTL coding best practices, synchronous design, timing constraints, and simulation-based verification techniques.
VHDL to Verilog and Verilog to VHDL
L_VV_UP VHDL to Verilog and Verilog to VHDL
Acquire the knowledge and skills required to transition from VHDL to Verilog or from Verilog to VHDL, by mastering the equivalences between the two languages for RTL design, hierarchical module structuring, and testbench development.
Software design with the Vitis tool
E_VITIS Software design of embedded systems with the Vitis™ tool
This course presents the tools and techniques needed to design and develop software using the Vitis™ unified software platform.
Software Design with PetaLinux™
E_PLNX Embedded Design with AMD PetaLinux Tools
Learn how to use the PetaLinux tool to create an embedded Linux distribution
Vivado AI Assistant
W_VIVADO_AI Using the AMD Ross™ Agentic AI Assistant for Vivado™ Design Suite
Discover and gain hands-on experience with the AMD Ross™ Agentic AI Assistant and agentic AI workflows to assist and automate key FPGA and Adaptive SoC design tasks, from design creation and analysis to timing closure, simulation, and hardware debug.
Ryzen AI
W_RYZENAI_CVML Local Computer Vision with AMD Ryzen™ AI and CVML
Discover how to develop local computer vision and perception applications using AMD Ryzen™ AI and the CVML library, while leveraging the GPU and NPU acceleration capabilities available on the platform.
Versal™
W_VER2 Introduction to the Versal™ Gen 2 Architecture
Discover the architecture and key innovations of AMD Versal™ Gen 2 devices to identify their application areas and capabilities.
W_US2VER Migrating from UltraScale+ FPGA designs to Versal SoC
Discover the key concepts and best practices for migrating an AMD UltraScale+™ FPGA design to an AMD Versal™ Adaptive SoC architecture, and understand the architectural changes, design impacts, and development flow adaptations involved in the migration process.
FPGA
W_USGEN2 Introduction to the Spartan™ and Kintex™ UltraScale+™ Gen 2 Architecture
Discover the architecture and key features of AMD Spartan™ and Kintex™ Gen 2 UltraScale+™ devices to understand their capabilities, architectural enhancements, and target application areas.
Migration
W_US2VER Migrating from UltraScale+ FPGA designs to Versal SoC
Discover the key concepts and best practices for migrating an AMD UltraScale+™ FPGA design to an AMD Versal™ Adaptive SoC architecture, and understand the architectural changes, design impacts, and development flow adaptations involved in the migration process.