VERSAL Xilinx
Trainings on Xilinx Adaptive SoC Versal™
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| A_START | Workshop : Getting Started with AMD Xilinx Versal ACAP Platform (French Language) 9h - 17h CET NEW | 1d | 0 € | |||
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DescriptionLive Online Workshop Event Read more |
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| ACAP_ARC | Designing with the Versal Adaptive SoC: Architecture and Methodology NEW | 4d | 4000 € | |||
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DescriptionLearn about Versal® Adaptive SoC architecture and design methodology. Read more |
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| AIE_INTR | Workshop : AI engines introduction of AMD Xilinx Versal (French Language) 9h - 17h CET NEW | 1d | 0 € | |||
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DescriptionLive Online Workshop Event Read more |
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| ACAP_AIE | Designing with Versal® AI Engine NEW | 4d | 4000 € | |||
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DescriptionProgram the AI engines, know the system design flow and the interfaces that can be used for data movement. Read more |
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Vitis Xilinx
Trainings on Vitis Unified Software Platform
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| AI_ACCEL | Accelerating Applications with the Vitis Unified Environment Software | 3d | 2700 € | |||
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DescriptionDevelop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications. Read more |
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| D_HLS | Vitis™ High Level Synthesis | 2d | 2000 € | |||
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DescriptionEnhance productivity using the Vitis™ HLS tool Read more |
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Xilinx SoC & MPSoC
Trainings on Zynq-7000® SoC and Zynq® UltraScale+™ MPSoC and design tools
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| E_ZAHS | The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components NEW | 4d | 3400 € | |||
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DescriptionLearn system architecture, hardware and software design of Zynq™-7000 and Zynq MPSoC components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104. Read more |
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| E_ZUPAHS | Zynq UltraScale+™ MPSoC : System Architecture, Hardware and Software Design NEW | 4d | 3400 € | |||
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DescriptionUnderstand Xilinx components Zynq UltraScale+™ architecture, hardware and software design. Read more |
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| E_PLNX | Embedded Design with Xilinx™ PetaLinux Tools | 3d | 2700 € | |||
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DescriptionLearn how to use the PetaLinux tool to create an embedded Linux distribution Read more |
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Xilinx FPGA
Trainings on Xilinx FPGA and Vivado Design Suite
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| F_VBASE | Designing FPGAs Using the Vivado Design Suite | 4d | 3400 € | |||
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DescriptionDesigning an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Read more |
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| F_STAXDC | Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado | 4d | 3400 € | |||
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DescriptionUnderstand XDC Timing constraints, Static timing analysis, good Xilinx FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite Read more |
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| F_DFX | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite NEW | 3d | 2700 € | |||
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DescriptionLearn how to build et assembly reconfigurable partitions to configure partially et dynamically a Xilinx™ component Read more |
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| F_US | Designing with the Xilinx™ UltraScale and UltraScale+ Families | 2d | 2000 € | |||
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DescriptionLearn how to effectively use Xilinx™ Ultrascale and UltraScale+ architectural resources Read more |
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| F_7SERIE | Designing with the Xilinx™ 7-Series Families | 2d | 2000 € | |||
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DescriptionLearn how to effectively use Xilinx™ 7 series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources Read more |
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Digital Signal Processing on RFSoC and FPGA
Trainings on Digital Signal Processing application designs on RFSoC and FPGA
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| C_RFSOC | Designing with the Zynq UltraScale+ RFSoC NEW | 3d | ||||
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DescriptionThis course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks. Read more |
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Connectivity
Trainings on FPGA connectivity
HDL Languages
Trainings on Hardware Description Languages
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| L_VHDL | VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design | 5d | 3000 € | |||
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DescriptionTraining on Xilinx FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (asynchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis) Read more |
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