AMD Vivado™ & Vitis HLS

Training courses on the FPGA design techniques

High-Level Synthesis with the Vitis Unified IDE New

Improve the productivity of components for Programmable Logic (FPGAs) using the Vitis™ HLS tool

Designing FPGAs Using the Vivado™

Designing an FPGA design, which includes creating a Vivado™ Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design.

Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™

Understand XDC Timing constraints, Static timing analysis, good AMD FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite

Designing with Dynamic Function eXchange (DFX) Using the Vivado™ New

Learn how to build et assembly reconfigurable partitions to configure partially et dynamically a AMD component