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    • Adaptive Versal™ Gen1 & Gen2
      • Versal™ Gen1 & Gen2 Architecture, Tools and methodology
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      • Software design with the Vitis tool
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      • Embedded design for AMD SoCs
    • Vivado™ & FPGA
      • AMD Vivado™ & Vitis HLS
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    • Digital Signal Processing on RFSoC and FPGA
      • Design with the Zynq™ UltraScale+ RFSoC
      • Digital Signal Processing on FPGA
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      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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PLANNING

Check out our training schedule

Up coming training sessions

The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components

March 02-05[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

Embedded Design with AMD PetaLinux Tools

April 01-03[register]

Lieu : EN LIGNE ---- CONFIRMATION EN ATTENTE

Designing with Versal™ AI Engine (AI, AIE-ML, AIE-MLv2)

April 07-10[register]

Lieu : EN LIGNE ---- CONFIRMATION EN ATTENTE

Designing with Versal™ Gen1 & Gen2 : Architecture, Tools and Methodology

April 13-16[register]

Lieu : EN LIGNE ---- CONFIRMATION EN ATTENTE

Adaptive Versal™

Adaptive Versal™

Gen1 & Gen2, NoC, GT, AI Engines, A72 & R5, ...

+
Embedded Softwares

Embedded Softwares

Vitis, PetaLinux, Yocto, ...

+
Adaptive SoC

Adaptive SoC

Zynq™, Zynq™ MPSoC

+
VIVADO FPGA

Vivado™ & FPGA

Vivado™, UltraScale+™, Vitis HLS

+
DSP

RFSoC & DSP

Digital Signal Processing on Zynq™ RFSoC and FPGA

+
HDL language

HDL language

VHDL, Verilog

+

INTRA TRAINING on demand

ACCESS TIME: 2 MONTHS
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QUALIOPI

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SATISFACTION

2025 : 94.4%

(129 Attendees)

2024 : 94.7%

(115 Attendees)

2023 : 91.8%

(97 Attendees)

2022 : 94.1%

(172 Attendees)
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