Trainer Profile

William Duluc, technical expert and AMD trainer

Drawing on hands-on experience designing and integrating FPGA and SoC systems, William Duluc turns real-world engineering challenges into training that engineering teams can apply directly.

FPGA and RTL design VHDL, Verilog and C/C++ SoC, MPSoC and RFSoC Versal adaptive platforms Digital signal processing and video Transceivers and high-speed serial links Vivado, Vitis, Vitis HLS and Model Composer
Field experience FPGA development, simulation, integration and validation before the training activity
Authorized AMD trainer official training and technical support on AMD/Xilinx technologies
Quality approach prerequisites, objectives, audience adaptation and satisfaction monitoring built into delivery

Professional distinctions

The quality of William Duluc's training delivery and his expertise in AMD/Xilinx technologies have been recognized on several occasions:

  • Recognized as best Xilinx, then AMD, trainer each year from 2017 to 2025.
  • Contribution to MVD Training receiving the AMD Authorized Training Provider Excellence Award in 2024.

Background

Professional milestones

Milestones supporting the technical and teaching competence used in the courses.

Since 2023

MVD Training CEO and AMD Trainer

Training provider management, quality-process oversight and teaching coordination, together with delivery of AMD trainings.

2017 - 2023

Authorized Xilinx trainer, then AMD trainer

Training activity development and technical delivery on FPGA, SoC, MPSoC, RFSoC, Versal and adaptive platforms; authorized Xilinx trainer from 2017, then AMD trainer following AMD's acquisition of Xilinx.

2009 - 2016

Design engineer and project manager, MVD Cores

VHDL and Verilog design of DVB-T, DVB-T2, ATSC and ISDB-T modulators, digital filters and high-speed serial links; project management, integration and technical support.

2008 - 2009

Design engineer, Multi Video Design

Completion of a DVB-T modulator and development of VHDL digital filters, building on projects started during the engineering degree.

2005 - 2008

ENSIL-ENSCI engineering degree

Engineering degree in electronics and telecommunications, complemented by digital modulation projects and the conversion of System Generator models to VHDL.

Technical competence

The background covers RTL design in VHDL/Verilog and C/C++, digital signal processing and video, high-speed serial links, SoC/MPSoC/RFSoC architectures, as well as implementation and simulation with Vivado, Vitis, Vitis HLS and Model Composer.

Teaching method

Sequences combine explanations, demonstrations, hands-on labs and discussion to connect concepts with design decisions made in engineering projects.

Need adaptation

Before and during training, attendee level, prerequisites and project context can be considered to orient examples, labs and answers.

Quality approach

Prerequisites, objectives, adaptation to the audience, learning-outcome assessment and satisfaction monitoring are integrated into the delivery of each course.