F_STAXDC

Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™

4 days · 28 hours Intermediate / Advanced Language: French Release date: 2024-11-15
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General training objective

Understand XDC Timing constraints, Static timing analysis, good AMD FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite

Target audience

Technicians and Engineers in Digital Electronics

Prerequisites

Intermediate knowledge in HDL language (VHDL or Verilog)
Experience with the Vivado™ Design suite and FPGAs.

Learning objectives and target skills

1 - Optimize HDL code to maximize FPGA resources and performance and use the UltraFast™ design methodology.
2 - Master the Vivado tool, apply timing constraints (XDC) and use appropriate timing reports.
3 - Identify key areas to optimize your design, minimize metastability issues and make your reset in your system more reliable
4 - Apply timing constraints on inputs/outputs to achieve performance targets
5 - Use advanced implementation options, such as incremental build flow, physical optimization techniques and re-entrant mode
6 - Use advanced techniques to improve design performance
7 - Debug a design during the start-up phase and use advanced debugging functions

Course content

Day 1
  • Objective 1
    • Introduction to FPGA architecture and Static Timing Analysis (STA) {Lectures}
    • HDL coding techniques {Lecture}
    • Ultra-fast design methodology: Board planning and design creation {Lectures}
  • Objective 2
    • Flow of the Vivado Design software suite {Lectures, Lab}
    • Vivado synthesis and implementation {Lecture}
    • Introduction to Vivado reports {Lecture}
Day 2
  • Objective 2
    • Baselining {Lecture}
    • Timing Constraints Editor {Lecture}
    • Clocking Resources {Lecture}
    • Introduction to Clock Constraints {Lecture}
    • Generated Clocks {Lecture, Lab}
    • Clock Group Constraints {Lecture}
    • Report Clock Interaction {Lecture}
    • Timing Summary Report {Lecture}
    • Setup and Hold Timing Analysis {Lecture}
    • I/O Constraints and Virtual Clocks {Lecture, Lab}
    • Introduction to Timing Exceptions {Lecture, Lab}
Day 3
  • Objective 3
    • Synchronous Design Techniques {Lecture}
    • Synchronization Circuits {Lecture, Lab}
    • Resets {Lecture}
    • Register Duplication {Lecture}
  • Objective 4
    • I/O Timing Scenarios {Lecture}
    • System-Synchronous I/O Timing {Lecture}
    • Source-Synchronous I/O Timing {Lecture, Lab}
    • I/O Logic Resources {Lecture}
    • Report Datasheet {Lecture}
    • Timing Constraints Priority {Lecture}
  • Objective 5
    • UltraFast Design Methodology: Implementation {Lecture}
    • Timing Closure Using Physical Optimization Techniques {Lecture}
    • Incremental Compile Flow {Lecture}
Day 4
  • Objective 6
    • QoR Reports Overview {Lecture, Lab}
    • Reducing Logic Delay {Lecture}
    • Reducing Net Delay {Lecture}
    • Improving Clock Skew {Lecture}
    • Improving Clock Uncertainty {Lecture, Lab}
    • Intelligent Design Runs (IDR) {Lecture, Lab}
    • Introduction to Floorplanning {Lecture}
  • Objective 7
    • Vivado Design Suite ECO Flow {Lecture, Lab}
    • JTAG to AXI Master Core {Lecture}
    • Trigger and Debug at Device Startup {Lecture}
    • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab}

Registration arrangements and access lead times

  • Registration requests can be made online, by email or by phone.
  • The prerequisites and the suitability of the training for the participant’s needs are verified by the trainer, by email or during a telephone interview.
  • Registration is confirmed after the prerequisites have been checked and subject to availability.
  • For inter-company sessions, registration is possible until 7 calendar days before the start of the course. Requests received after this deadline may be considered on a case-by-case basis, depending on organisational possibilities.
  • For in-company sessions, the average lead time for implementation is approximately 2 months from the date of the request, depending on the availability of the client, the trainer and any adaptations required.
  • A registration confirmation and the information necessary to attend the course are sent before the session begins.

Teaching staff

The training course is delivered by William Duluc, AMD Authorized Trainer since 2017, an electronics and telecommunications engineer, an expert in AMD technologies since 2009. His experience combines digital system design, FPGA and embedded software development, technical project management, and professional training on Xilinx and subsequently AMD technologies.
His main areas of expertise include:
  • AMD FPGAs: VHDL and Verilog languages, RTL design, integration and validation of digital systems;
  • AMD SoCs and MPSoCs: C/C++ development, hardware and software architectures, design and integration of embedded systems;
  • AMD DSP and RFSoC: high-level synthesis (HLS), MATLAB/Simulink, digital signal processing and radio-frequency architectures;
  • AMD Versal: AI Engines, adaptive architectures and heterogeneous system design.

Accessibility

People with disabilities are invited to contact MVD Training before registering so that possible training adjustments can be considered. Educational, technical, or organisational adaptations are reviewed on a case-by-case basis, taking into account the participant's needs, the technical requirements, and the training objectives. Where relevant, this review may be carried out with support from AGEFIPH.

Teaching resources

Inter-company online training:
  • Live virtual classroom delivered via Cisco Webex;
  • Training materials provided in PDF format;
  • Technical demonstrations conducted by the trainer;
  • Individual practical exercises carried out on a training workstation accessed remotely via RealVNC;
  • Guidance and technical support provided by the trainer during the exercises.
Intra-company on-site training at the client’s premises: Equipment and logistical arrangements must be agreed with the client before the training course.
  • Resources to be provided by the client:
    • Suitable training room;
    • Projector or presentation screen;
    • Whiteboard;
    • One computer per participant, equipped with the required AMD tools.
  • Resources provided by MVD Training:
    • Training materials in PDF format;
    • Presentations, technical demonstrations and practical exercises;
    • Files, examples and resources required for the practical exercises;
    • Loan of computer equipment available upon request and subject to availability.

Technical resources and equipment

Inter-company online training:
  • Computer running a 64-bit operating system;
  • High-speed and stable internet connection;
  • Webcam and headset with microphone;
  • Cisco Webex application Webex de Cisco
AMD tools access arrangements:
The practical exercises are carried out using one of the following two options, as agreed with the trainer:
  • Option 1 – Remote access: REALVNC
    Use of the RealVNC Viewer application to access the practical training workstation made available remotely by MVD Training.
  • Option 2 – Local use: Vitis
    Installation of the AMD software tools required for the training course on the participant’s computer. The version to be used must be specified and approved with the trainer before the start of the session.
Intra-company on-site training at the client’s premises:
  • Computer running a 64-bit operating system;
  • Installation of the AMD software tools required for the training course. The version to be used must be specified and approved with the trainer before the start of the session.

Teaching methods, assessment and recognition

  • Teaching methods:
    • A combination of theoretical instruction, technical questionnaires and practical exercises completed individually on a computer.
  • Training monitoring:
    • Attendance sheet signed by both the participant and the trainer.
  • Assessment of learning outcomes and progress:
    • Continuous assessment of learning outcomes and learner progress through technical quizzes, hands-on laboratory exercises, and trainer observation against the targeted competencies.
  • Satisfaction assessment:
    • At the end of the training course: satisfaction questionnaire completed by the participant.
  • Three-month follow-up evaluation:
    • Three months after the training course: questionnaire assessing how the acquired skills have been applied in the workplace.
  • Training recognition:
    • Training certificate stating the results of the learning assessment, issued to the participant.
    • Certificate of completion issued to the employer or the organisation commissioning the training.

Partner

MVD Training is an AMD Authorized Training Provider. Training courses are delivered by an AMD Authorized Trainer and are based on official AMD training materials.
AMD Authorized Training Provider