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    • AMD Versal™
      • Versal™ Architecture, NoC and methodology
      • Versal™ AI Engine
    • AMD Vitis™
      • Software design of embedded systems with the Vitis tool
      • Accelerating Applications with the Vitis
      • High-Level Synthesis with the Vitis HLS Tool
    • AMD SoCs
      • Embedded design for AMD SoCs
      • MPSoC Zynq™ UltraScale+
      • PetaLinux™
    • AMD FPGA
      • AMD Vivado™
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
      • DSP Functions
    • Connectivity
      • Multi-Gigabit Transceivers
      • PCI Express
    • HDL Languages
      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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MVD Training

Check out our training schedule Ask us for customized training

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Up coming training sessions

Designing with the Adaptive SoC Versal™ : Architecture and Methodology

October 02-05[register]

EN LIGNE

Workshop : AI engines introduction of AMD Versal™ (French Language) 9h - 17h CET

October 06[register]

EN LIGNE

Designing with Versal™ AI Engine

October 16-19[register]

EN LIGNE

Designing FPGAs Using the Vivado™

November 06-09[register]

EN LIGNE

Training sessions schedule

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AMD Versal™

AMD Versal™

Versal™ Adaptive SoC

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AMD Vitis™

AMD Vitis™

Vitis™ Unified Software Platform

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AMD SoC

AMD SoC

Zynq™, Zynq™ MPSoC, PetaLinux

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AMD FPGA

AMD FPGA

UltraScale™, Vivado™, 7-Serie™,...

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DSP

RFSoC & DSP

Digital Signal Processing on Zynq™ RFSoC and FPGA

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Connectivity

Connectivity

Transceivers, PCI-e

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HDL language

HDL language

Hardware Description Language

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