Adaptive Versal™
Training courses on Adaptive SoC Versal™
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| ACAP_ARC | Designing with the Adaptive SoC Versal™ : Architecture, Tools and Methodology NEW | 4 days | 3600 € | |||
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DescriptionLearn about Versal™ architecture and design methodology. Read more |
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| VER_NOC | Designing with the Network On Chip of AMD Versal™ NEW | 1 day | 1200 € | |||
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DescriptionLearn how to use the NoC to efficiently move your data through Versal™ components. Read more |
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| VER_TRX | Designing with Versal™ Serial Transceivers NEW | 2 days | 2200 € | |||
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DescriptionLearn how to use Versal™ GTY and GTM serial transceivers Read more |
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| VER_PCIE | Designing an Integrated PCI Express® System for Versal™ NEW | 2 days | 2200 € | |||
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DescriptionIdentify and construct a PCI Express® system on Versal™ Read more |
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Vitis™
Trainings on Vitis Unified Software Platform
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| AI_ACCEL | Accelerating Applications with the Vitis™ Unified Environment Software | 3 days | 3000 € | |||
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DescriptionDevelop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications. Read more |
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Adaptive SoCs
Trainings on Zynq-7000™ SoC and Zynq MPSoC™ and design tools
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| E_ZAHS | The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components NEW | 4 days | 3600 € | |||
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DescriptionLearn system architecture, hardware and software design of Zynq™-7000, Zynq™ MPSoC and Versal™ components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104. Read more |
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Vivado™ & FPGA
Training courses on Vivado™ Design Suite and AMD FPGA
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| F_VBASE | Designing FPGAs Using the Vivado™ | 4 days | 3600 € | |||
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DescriptionDesigning an FPGA design, which includes creating a Vivado™ Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Read more |
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| F_STAXDC | Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™ | 4 days | 3600 € | |||
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DescriptionUnderstand XDC Timing constraints, Static timing analysis, good AMD FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite Read more |
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| F_DFX | Designing with Dynamic Function eXchange (DFX) Using the Vivado™ NEW | 3 days | 3000 € | |||
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DescriptionLearn how to build et assembly reconfigurable partitions to configure partially et dynamically a AMD component Read more |
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| F_SU | Designing with the AMD UltraScale+™ Families (Spartan™ included) NEW | 2 days | 2200 € | |||
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DescriptionLearn how to effectively use AMD UltraScale+™ architectural resources Read more |
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| F_7SERIE | Designing with the AMD 7-Series Families | 2 days | ||||
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DescriptionLearn how to effectively use AMD7-series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources Read more |
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| C_TRX | Designing with Serial Transceivers | 2 days | ||||
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DescriptionLearn how to use serial transceivers in your UltraScale™, UltraScale+™ FPGA or Zynq™ UltraScale + MPSoC. Read more |
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| C_PCIE | Designing an Integrated PCI Express System | 2 days | 2200 € | |||
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DescriptionUnderstand the Xilinx™ FPGA hardware design using AMD PCI-e core Read more |
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Digital Signal Processing on RFSoC and FPGA
Trainings on Digital Signal Processing application designs on RFSoC and FPGA
HDL Languages
Trainings on Hardware Description Languages
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| L_VHDL | VHDL Logical Synthesis and Simulation for AMD FPGA design | 5 days | 4400 € | |||
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DescriptionUnderstand AMD FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (synchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis) Read more |
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