W_VER2
Introduction to the Versal™ Gen 2 Architecture
General objective of the workshop
Discover the architecture and key innovations of AMD Versal™ Gen 2 devices to identify their application areas and capabilities.
Target audience
- FPGA and embedded systems engineers.
- Hardware and software architects.
- Technical project managers wishing to learn about AMD Versal™ Gen 2 devices.
Prerequisites
- General knowledge of FPGA or SoC architectures.
- Basic knowledge of AMD/Xilinx devices and tools (Vivado™, Zynq™, Versal™, or equivalent) is recommended.
- Prior experience with AMD/Xilinx tools or devices is recommended.
Workshop objectives
- Identify the key architectural enhancements of AMD Versal™ Gen 2 devices compared with previous generations.
- Explain the role and key features of the Processing System in Versal™ Gen 2 devices.
- Describe the main capabilities of the AI Engine-ML v2 architecture and its application areas.
- Identify the benefits of DDR5 memory interfaces in Versal™ Gen 2 architectures.
- Describe the capabilities of the integrated multimedia blocks and their use cases.
- Identify the application areas for which AMD Versal™ Gen 2 devices are a suitable solution.
Workshop content
Day 1
- Processing System {Lecture}
- AIE-ML v2 Architecture Overview {Lecture}
- Designing with DDR5 {Lecture}
- Multimedia Hard Blocks {Lecture}
Registration arrangements and access lead times
- Registration requests can be made online, by email or by phone.
- Registration is confirmed after subject to availability.
- A registration confirmation and the information necessary to attend the workshop are sent before the session begins.
Teaching staff
The training course is delivered by William Duluc, AMD Authorized Trainer since 2017, an electronics and telecommunications engineer, an expert in AMD technologies since 2009. His experience combines digital system design, FPGA and embedded software development, technical project management, and professional training on Xilinx and subsequently AMD technologies.
His main areas of expertise include:
- AMD FPGAs: VHDL and Verilog languages, RTL design, integration and validation of digital systems;
- AMD SoCs and MPSoCs: C/C++ development, hardware and software architectures, design and integration of embedded systems;
- AMD DSP and RFSoC: high-level synthesis (HLS), MATLAB/Simulink, digital signal processing and radio-frequency architectures;
- AMD Versal: AI Engines, adaptive architectures and heterogeneous system design.
Accessibility
People with disabilities are invited to contact MVD Training before registering so that possible training adjustments can be considered. Educational, technical, or organisational adaptations are reviewed on a case-by-case basis, taking into account the participant's needs, the technical requirements, and the training objectives. Where relevant, this review may be carried out with support from AGEFIPH.
Teaching resources
- Live virtual classroom delivered via Cisco Webex;
- Training materials provided in PDF format;
- Technical demonstrations conducted by the trainer;
Technical resources and equipment
- Computer running a 64-bit operating system;
- High-speed and stable internet connection;
- Webcam and headset with microphone;
- Cisco Webex application
Partner
MVD Training is an AMD Authorized Training Provider. Workshops are delivered by an AMD Authorized Trainer and are based on official AMD training materials.
Notes
This workshop is a technical presentation and demonstration service. It does not constitute a vocational training activity and does not include any assessment of learning outcomes or the issuance of a training certificate.