W_US2VER

Migrating from UltraScale+ FPGA designs to Versal SoC

0.5 day · 3.5 hours Language: French Release date: 2026-07-31
Register for an inter-company session

General objective of the workshop

Discover the key concepts and best practices for migrating an AMD UltraScale+™ FPGA design to an AMD Versal™ Adaptive SoC architecture, and understand the architectural changes, design impacts, and development flow adaptations involved in the migration process.

Target audience

  • FPGA and embedded systems engineers.
  • Hardware and software architects.
  • Designers currently developing with AMD UltraScale+™ devices.
  • Technical project managers planning a migration to AMD Versal™ Adaptive SoCs.

Prerequisites

  • General knowledge of AMD FPGA architectures.
  • Prior experience with AMD UltraScale+™ or Zynq™ UltraScale+™ MPSoC devices is recommended.
  • Basic familiarity with AMD Vivado™ and FPGA design flows is recommended.

Workshop objectives

  • Identify the main architectural differences between AMD UltraScale+™ devices and AMD Versal™ Adaptive SoCs.
  • Explain the key steps involved in migrating an existing design to a Versal™ architecture.
  • Describe the evolution of the design flow and the associated development tools.
  • Explain the fundamental concepts of the Network-on-Chip (NoC) architecture and its impact on system design.
  • Identify the main considerations when migrating programmable logic (PL) designs.
  • Compare the Processing System architectures of UltraScale+™ and Versal™ devices.

Workshop content

Day 1
  • Architecture Overview for Existing Users {Lecture}
  • System Design Migration Approach {Lecture}
  • Design Tool Flow {Lecture}
  • NoC Introduction and Concepts {Lecture}
  • Programmable Logic Design Migration Considerations {Lecture}
  • Processing System Comparison {Lecture}

Registration arrangements and access lead times

  • Registration requests can be made online, by email or by phone.
  • Registration is confirmed after subject to availability.
  • A registration confirmation and the information necessary to attend the workshop are sent before the session begins.

Teaching staff

The training course is delivered by William Duluc, AMD Authorized Trainer since 2017, an electronics and telecommunications engineer, an expert in AMD technologies since 2009. His experience combines digital system design, FPGA and embedded software development, technical project management, and professional training on Xilinx and subsequently AMD technologies.
His main areas of expertise include:
  • AMD FPGAs: VHDL and Verilog languages, RTL design, integration and validation of digital systems;
  • AMD SoCs and MPSoCs: C/C++ development, hardware and software architectures, design and integration of embedded systems;
  • AMD DSP and RFSoC: high-level synthesis (HLS), MATLAB/Simulink, digital signal processing and radio-frequency architectures;
  • AMD Versal: AI Engines, adaptive architectures and heterogeneous system design.

Accessibility

People with disabilities are invited to contact MVD Training before registering so that possible training adjustments can be considered. Educational, technical, or organisational adaptations are reviewed on a case-by-case basis, taking into account the participant's needs, the technical requirements, and the training objectives. Where relevant, this review may be carried out with support from AGEFIPH.

Teaching resources

  • Live virtual classroom delivered via Cisco Webex;
  • Training materials provided in PDF format;
  • Technical demonstrations conducted by the trainer;

Technical resources and equipment

  • Computer running a 64-bit operating system;
  • High-speed and stable internet connection;
  • Webcam and headset with microphone;
  • Cisco Webex application Webex de Cisco

Partner

MVD Training is an AMD Authorized Training Provider. Training courses are delivered by an AMD Authorized Trainer and are based on official AMD training materials.
AMD Authorized Training Provider

Notes

This workshop is a technical presentation and demonstration service. It does not constitute a vocational training activity and does not include any assessment of learning outcomes or the issuance of a training certificate.