W_USGEN2

Introduction to the Spartan™ and Kintex™ UltraScale+™ Gen 2 Architecture

0.5 day · 3.5 hours Language: French Release date: 2026-07-31
Register for an inter-company session

General objective of the workshop

Discover the architecture and key features of AMD Spartan™ and Kintex™ Gen 2 UltraScale+™ devices to understand their capabilities, architectural enhancements, and target application areas.

Target audience

  • FPGA and embedded systems engineers.
  • Hardware architects and digital design engineers.
  • Technical project managers interested in discovering AMD Spartan™ and Kintex™ Gen 2 UltraScale+™ devices.

Prerequisites

  • General knowledge of FPGA architectures.
  • Basic familiarity with AMD/Xilinx devices (Vivado™, UltraScale™, UltraScale+™ or equivalent) is recommended.
  • Prior experience with AMD/Xilinx tools or devices is recommended.

Workshop objectives

  • Identify the main characteristics of the AMD UltraScale+™ device families and their positioning within the AMD adaptive computing portfolio.
  • Describe the architecture of AMD Spartan™ and Kintex™ Gen 2 UltraScale+™ devices.
  • Explain the role and key features of the integrated I/O resources.
  • Identify the main capabilities of the high-speed transceivers and integrated PCI Express® interfaces.
  • Describe the configuration mechanisms and key security features available in AMD Spartan™ and Kintex™ Gen 2 UltraScale+™ devices.

Workshop content

Day 1
  • Introduction to the UltraScale+™ Families {Lecture}
  • Introduction to the Spartan™ and Kintex Gen 2 UltraScale+™ Architectures {Lecture}
  • I/O Resources {Lecture}
  • Transceivers and PCIe {Lecture}
  • Configuration and Security {Lecture}

Registration arrangements and access lead times

  • Registration requests can be made online, by email or by phone.
  • Registration is confirmed after subject to availability.
  • A registration confirmation and the information necessary to attend the workshop are sent before the session begins.

Teaching staff

The training course is delivered by William Duluc, AMD Authorized Trainer since 2017, an electronics and telecommunications engineer, an expert in AMD technologies since 2009. His experience combines digital system design, FPGA and embedded software development, technical project management, and professional training on Xilinx and subsequently AMD technologies.
His main areas of expertise include:
  • AMD FPGAs: VHDL and Verilog languages, RTL design, integration and validation of digital systems;
  • AMD SoCs and MPSoCs: C/C++ development, hardware and software architectures, design and integration of embedded systems;
  • AMD DSP and RFSoC: high-level synthesis (HLS), MATLAB/Simulink, digital signal processing and radio-frequency architectures;
  • AMD Versal: AI Engines, adaptive architectures and heterogeneous system design.

Accessibility

People with disabilities are invited to contact MVD Training before registering so that possible training adjustments can be considered. Educational, technical, or organisational adaptations are reviewed on a case-by-case basis, taking into account the participant's needs, the technical requirements, and the training objectives. Where relevant, this review may be carried out with support from AGEFIPH.

Teaching resources

  • Live virtual classroom delivered via Cisco Webex;
  • Training materials provided in PDF format;
  • Technical demonstrations conducted by the trainer;

Technical resources and equipment

  • Computer running a 64-bit operating system;
  • High-speed and stable internet connection;
  • Webcam and headset with microphone;
  • Cisco Webex application Webex de Cisco

Partner

MVD Training is an AMD Authorized Training Provider. Training courses are delivered by an AMD Authorized Trainer and are based on official AMD training materials.
AMD Authorized Training Provider

Notes

This workshop is a technical presentation and demonstration service. It does not constitute a vocational training activity and does not include any assessment of learning outcomes or the issuance of a training certificate.