W_AIASSISTANT

FPGA and Adaptive SoC Design Automation with Vivado AI Assistant

1 day · 7 hours Language: French Release date: 2026-09-10
Register for an inter-company session

General objective of the workshop

Discover and gain hands-on experience with the AMD Vivado™ AI Assistant and agentic AI workflows to assist and automate key FPGA and Adaptive SoC design tasks, from design creation and analysis to design closure.

Target audience

  • FPGA and Adaptive SoC designers
  • Hardware and embedded systems engineers
  • Vivado™ Design Suite users interested in AI-assisted design workflows
  • Technical leads and architects looking to evaluate the use of agentic AI in FPGA and Adaptive SoC development

Prerequisites

  • Basic knowledge of FPGA or Adaptive SoC design concepts
  • Familiarity with the AMD Vivado™ Design Suite and the standard FPGA design flow
  • Basic understanding of HDL-based design (VHDL or Verilog) is recommended
  • No prior experience with AI assistants or agentic AI is required

Workshop objectives

  • Understand the key features of AMD Vivado™ AI Assistant and its integration into the FPGA and Adaptive SoC design flow.
  • Use and configure a knowledge base to improve interactions with Vivado AI Assistant.
  • Use the assistant to facilitate design entry and creation, as well as the analysis and interpretation of design results.

Workshop content

Day 1
  • Introduction to AMD Vivado™ AI Assistant {Lecture}
  • Agentic AI Workflows for FPGA and Adaptive SoC Design {Lecture}
  • Demo 1 – Getting Started and Knowledge Base Setup
  • Demo 2 – Design Capture
  • Demo 3 – Design Analysis
  • Demo 4 – Design Closure

Registration arrangements and access lead times

  • Registration requests can be made online, by email or by phone.
  • Registration is confirmed after subject to availability.
  • A registration confirmation and the information necessary to attend the workshop are sent before the session begins.

Teaching staff

The training course is delivered by William Duluc, AMD Authorized Trainer since 2017, an electronics and telecommunications engineer, an expert in AMD technologies since 2009. His experience combines digital system design, FPGA and embedded software development, technical project management, and professional training on Xilinx and subsequently AMD technologies.
His main areas of expertise include:
  • AMD FPGAs: VHDL and Verilog languages, RTL design, integration and validation of digital systems;
  • AMD SoCs and MPSoCs: C/C++ development, hardware and software architectures, design and integration of embedded systems;
  • AMD DSP and RFSoC: high-level synthesis (HLS), MATLAB/Simulink, digital signal processing and radio-frequency architectures;
  • AMD Versal: AI Engines, adaptive architectures and heterogeneous system design.

Accessibility

People with disabilities are invited to contact MVD Training before registering so that possible training adjustments can be considered. Educational, technical, or organisational adaptations are reviewed on a case-by-case basis, taking into account the participant's needs, the technical requirements, and the training objectives. Where relevant, this review may be carried out with support from AGEFIPH.

Teaching resources

  • Live virtual classroom delivered via Cisco Webex;
  • Training materials provided in PDF format;
  • Technical demonstrations conducted by the trainer;

Technical resources and equipment

  • Computer running a 64-bit operating system;
  • High-speed and stable internet connection;
  • Webcam and headset with microphone;
  • Cisco Webex application Webex de Cisco

Partner

MVD Training is an AMD Authorized Training Provider. Training courses are delivered by an AMD Authorized Trainer and are based on official AMD training materials.
AMD Authorized Training Provider

Notes

This workshop is a technical presentation and demonstration service. It does not constitute a vocational training activity and does not include any assessment of learning outcomes or the issuance of a training certificate.