AIE_DSGN

Designing with Versal™ AI Engine (AI, AIE-ML, AIE-MLv2)

4 days · 28 hours Intermediate / Advanced Language: French Release date: 2026-08-08
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General training objective

Acquire the knowledge and skills required to design, program, analyze, and optimize applications using AMD Versal™ AI Engines, by leveraging kernel-based and dataflow graph programming models as well as associated DSP libraries.

Target audience

  • FPGA/SoC engineers and developers;
  • Digital Signal Processing (DSP) engineers;
  • C/C++ developers wishing to leverage AMD Versal™ AI Engines;
  • System architects working with AMD Versal™ platforms;
  • Designers wishing to develop or optimize compute-intensive algorithms on AI Engines.

Prerequisites

  • Have a working knowledge of C/C++;
  • Understand the basic principles of Digital Signal Processing (DSP) and/or vector computing;
  • Have general knowledge of FPGA and SoC architectures;
  • Have basic knowledge of the AMD Vitis™ development environment.

Learning objectives and target skills

1 - Identify the architecture of AMD Versal™ devices and master the system design flow in order to understand the role of AI Engines within a complete architecture and implement the different stages of the development process.
2 - Describe and differentiate AI Engine, AI Engine-ML, and AI Engine-ML v2 architectures, including their computing resources, memory organization, and data movement mechanisms.
3 - Develop and optimize AI Engine compute kernels using scalar and vector data types, AI Engine APIs, I/O buffers and streams, as well as compiler directives and optimization techniques.
4 - Design, program, analyze, and debug an AI Engine application based on a dataflow graph, including multiple kernels, runtime parameters and, for AI Engine-ML architectures, the use of memory tiles.
5 - Implement AI Engine DSP library functions to integrate optimized digital signal processing operations into a Versal™ application.

Course content

Day 1
  • Objective 1
    • Overview of Versal Architecture {Lecture}
    • System design flow {Lecture, Labs}
  • Objective 2
    • Versal AI Engine Architecture {Lecture}
    • Versal AI Engine Memory and Data Movement {Lecture}
    • Versal AI-ML Engine Architecture {Lecture}
    • Versal AI-MLv2 Engine Architecture {Lecture}
  • Objective 3
    • Scalar and Vector Data Types {Lecture}
    • AI Engine APIs {Lecture, Labs}
Day 2
  • Objective 3
    • I/O Buffers and Streaming Data APIs {Lecture}
    • Design Analysis : Vitis Analyzer {Lecture}
    • The Programming Model: Single Kernel {Lecture, Lab}
    • Introduction to AI Engine APIs for Arithmetic Operations {Lecture}
    • AI Engine Kernel Optimization – Compiler Directives {Lecture}
    • AIE Kernel Optimization – Coding Style {Lecture}
    • The Programming Model: Single Kernel Using Vector Data Types {Lab}
Day 3
  • Objective 4
    • The Programming Model: Introduction to the Data Flow Graph {Lecture}
    • The Programming Model: Multiple Kernels Using Graphs {Lecture, Lab}
    • AI Engine Application Debug and Trace {Lecture}
    • Advanced Graph Input Specifications {Lecture}
    • Graph Input and Runtime Parameters {Lecture, Lab}
Day 4
  • Objective 4
    • AIE-ML Memory Tiles and Programming {Lecture, Labs}
  • Objective 5
    • AI Engine DSP Library Overview {Lecture, Labs}
  • Appendixes(optional)
    • AI Engine Symmetric and Asymmetric Filter Implementation {Lecture, Labs}

Registration arrangements and access lead times

Registration requests can be made online, by email or by phone.
The prerequisites and the suitability of the training for the participant’s needs are verified by the trainer, by email or during a telephone interview.
Registration is confirmed after the prerequisites have been checked and subject to availability.
For inter-company sessions, registration is possible until 7 calendar days before the start of the course. Requests received after this deadline may be considered on a case-by-case basis, depending on organisational possibilities.
For in-company sessions, the average lead time for implementation is approximately 2 months from the date of the request, depending on the availability of the client, the trainer and any adaptations required.
A registration confirmation and the information necessary to attend the course are sent before the session begins.

Teaching staff

The training course is delivered by William Duluc, AMD Authorized Trainer since 2017, an electronics and telecommunications engineer, an expert in AMD technologies since 2009. His experience combines digital system design, FPGA and embedded software development, technical project management, and professional training on Xilinx and subsequently AMD technologies.
His main areas of expertise include:
  • AMD FPGAs: VHDL and Verilog languages, RTL design, integration and validation of digital systems;
  • AMD SoCs and MPSoCs: C/C++ development, hardware and software architectures, design and integration of embedded systems;
  • AMD DSP and RFSoC: high-level synthesis (HLS), MATLAB/Simulink, digital signal processing and radio-frequency architectures;
  • AMD Versal: AI Engines, adaptive architectures and heterogeneous system design.

Accessibility

People with disabilities are invited to contact MVD Training before registering so that possible training adjustments can be considered. Educational, technical, or organisational adaptations are reviewed on a case-by-case basis, taking into account the participant's needs, the technical requirements, and the training objectives. Where relevant, this review may be carried out with support from AGEFIPH.

Teaching resources

Formation Inter-entreprise à distance :
  • Live virtual classroom delivered via Cisco Webex;
  • Training materials provided in PDF format;
  • Technical demonstrations conducted by the trainer;
  • Individual practical exercises carried out on a training workstation accessed remotely via RealVNC;
  • Guidance and technical support provided by the trainer during the exercises.
Intra-company on-site training at the client’s premises: Equipment and logistical arrangements must be agreed with the client before the training course.
  • Resources to be provided by the client:
    • Suitable training room;
    • Projector or presentation screen;
    • Whiteboard;
    • One computer per participant, equipped with the required AMD tools.
  • Resources provided by MVD Training:
    • Training materials in PDF format;
    • Presentations, technical demonstrations and practical exercises;
    • Files, examples and resources required for the practical exercises;
    • Loan of computer equipment available upon request and subject to availability.

Technical resources and equipment

Inter-company remote training:
  • Computer running a 64-bit operating system;
  • High-speed and stable internet connection;
  • Webcam and headset with microphone;
  • Cisco Webex application Webex de Cisco
AMD tools access arrangements:
The practical exercises are carried out using one of the following two options, as agreed with the trainer:
  • Option 1 – Remote access: REALVNC
    Use of the RealVNC Viewer application to access the practical training workstation made available remotely by MVD Training.
  • Option 2 – Local use: Vitis
    Installation of the AMD software tools required for the training course on the participant’s computer. The version to be used must be specified and approved with the trainer before the start of the session.
Intra-company on-site training at the client’s premises:
  • Computer running a 64-bit operating system;
  • Installation of the AMD software tools required for the training course. The version to be used must be specified and approved with the trainer before the start of the session.

Teaching methods, assessment and recognition

  • Teaching methods:
    • A combination of theoretical instruction, technical questionnaires and practical exercises completed individually on a computer.
  • Training monitoring:
    • Attendance sheet signed by both the participant and the trainer.
  • Assessment of learning outcomes and progress:
    • Continuous assessment of learning outcomes and learner progress through technical quizzes, hands-on laboratory exercises, and trainer observation against the targeted competencies.
  • Satisfaction assessment:
    • At the end of the training course: satisfaction questionnaire completed by the participant.
  • Three-month follow-up evaluation:
    • Three months after the training course: questionnaire assessing how the acquired skills have been applied in the workplace.
  • Training recognition:
    • Training certificate stating the results of the learning assessment, issued to the participant.
    • Certificate of completion issued to the employer or the organisation commissioning the training.

Partner

MVD Training is an AMD Authorized Training Provider. Training courses are delivered by an AMD Authorized Trainer and are based on official AMD training materials.
AMD Authorized Training Provider