Accelerating Applications with the Vitis™ Unified Environment Software

(ref.AI_ACCEL)
TIME

3 days - 21 hours   

Target objectives and skills

  • 1 - Explain how the Vitis unified software environment helps software developers
  • 2 - Describe how the FPGA architecture lends itself to parallel computing, as well as the ALVEO boards
  • 3 - Describe the Vitis execution model (OpenCL API)
  • 4 - Profile the design using the Vitis analysis tool
  • 5 - Create kernels from C, C++ or RTL IP using the RTL kernel creation wizard
  • 6 - Apply host code and kernel optimization techniques
  • 7 - Describe existing libraries and create an extensible platform

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • People with disabilities may have special training needs. Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability. Don't hesitate to to discuss your requirements.agefiph

Prerequisites

  • Basic knowledge of AMD FPGA architecture
  • Comfort with the C/C++ programming language
  • Software development flow

Course content

Day 1

Objective 1

  • Introduction to the Vitis Unified Software Platform {Lecture}
  • Vitis IDE Tool Overview {Lecture, Labs}
  • Vitis Command Line Flow {Lecture, Labs}

Objective 2

  • Introduction to Hardware Acceleration {Lecture}
  • Alveo Data Center Accelerator Cards Overview {Lecture}
  • Getting Started with Alveo Data Center Accelerator Cards {Lecture}

Day 2

Objective 3

  • Vitis Execution Model and XRT {Lecture, Labs}
  • Synchronization {Lecture, Lab}
  • NDRanges {Lecture}

Objective 4

  • Profiling {Lecture}
  • Debugging {Lecture}

Objective 5

  • Introduction to C/C++ based Kernels {Lecture, Lab}

Day 3

Objective 5

  • Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab}

Objective 6

  • Optimization Methodology {Lecture}
  • C/C++ based Kernel Optimization {Lecture}
  • Host Code Optimization {Lecture}
  • Optimizing the Performance of the Design {Lecture, Lab}

Objective 7

  • Vitis Accelerated Libraries {Lecture}
  • Creating a Vitis Embedded Acceleration Platform (Edge) {Lecture}

Teaching methods and support - Assessment and recognition

  • Teaching methods :
    • Alternating lectures, technical questionnaires and exercises on individual machines.
  • Pedagogical follow-up :
    • Signed attendance sheet
  • Pedagogical assessment :
    • Continuous assessment and progress sheet :
      • Technical questionnaire
      • Practical work results
      • Validation of objectives
  • Satisfaction survey :
    • At the end of training: assessment form completed by the trainee
    • At 3 months: evaluation form completed by the trainee after application to the company
  • Certificate :
    • Training certificate with assessment of learning provided to trainee
    • Certificate of completion provided to employer

Teaching Methods

  • Inter-company online training :
    • Fast Internet connection, webcam, headset
    • Presentation by Webex by Cisco Webex de Cisco
    • Provision of course material in PDF format
    • Labs on individual Cloud PC by RealVNC REALVNC
  • Intra-company face-to-face training on customer site : (details to be confirmed prior to training)
    • Suggested supply by the customer :
      • Training room
      • Video projector
      • Whiteboard
      • Individual PC with AMD tools
    • Provided by MVD Training :
      • Course material in PDF format
      • Practical work on individual PCs (loan of equipment available on request)

Recommended computer hardware

  • Inter-company online training :
    • Recent computer OS Linux or Windows 64-bits
    • Fast Internet, webcam, headset
    • Software tool WebEx Cisco
    • AMD remote tools :
    • AMD local tools :
      • Software tool AMD Vitis 2022.2
  • Face-to-face training on customer site :
    • Recent computer OS Linux or Windows 64-bits
    • Software tool AMD Vitis 2022.2

Teaching staff

  • William Duluc, Electronics and Telecoms Engineer, AMD Expert since 2009 and AMD Trainer since 2017 :
    • Expert AMD FPGA - Language VHDL/Verilog - RTL Design
    • Expert AMD SoC & MPSoC - Language C/C++ - System Design
    • Expert DSP & AMD RFSoC – HLS - Matlab - Design DSP RF
    • Expert AMD Versal – AI Engines – Heteregenous System Architect

Certified Partner

xilinx atp

Notes

  • Release date: 15/11/2024