Designing with Serial Transceivers
(ref.C_TRX)
2 days - 14 hours
Target objectives and skills
- 1 - Describe and utilize the ports and attributes of the serial transceivers in the UltraScale FPGAs
- 2 - Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
- 3 - Effectively utilize the coding, pre-emphasis and linear equalization features of the gigabit transceivers
- 4 - Use the IBERT design to verify transceiver links on real hardware
- 5 - Access reference material and debugging tools for your designs
Concerned public
- Technicians and Engineers in Digital Electronics
- All our training courses are given at a distance and are accessible to people with reduced mobility.
- People with disabilities may have special training needs. Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability. Don't hesitate to to discuss your requirements.
Prerequisites
- Verilog or VHDL experience
- Basic knowledge of FPGA architecture and Vivado™ implementation tools is helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Course content
Objective 1
- UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview {Lecture}
- UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets {Lecture}
Objective 2
- Transceiver Wizard Overview {Lecture, Lab}
- Transceiver Simulation {Lecture, Lab}
- Transceiver Implementation {Lecture, Lab}
Objective 3
- PCS Layer General Functionality {Lecture}
- PCS Layer Encoding {Lecture, Lab}
Objective 4
- PMA Layer Details {Lecture}
- PMA Layer Optimization {Lecture, Lab}
Objective 5
- Transceiver Test and Debugging {Lecture}
- Transceiver Board Design Considerations {Lecture}
- Transceiver Application Examples {Lecture}
Teaching methods and support - Assessment and recognition
- Teaching methods :
- Alternating lectures, technical questionnaires and exercises on individual machines.
- Pedagogical follow-up :
- Signed attendance sheet
- Pedagogical assessment :
- Continuous assessment and progress sheet :
- Technical questionnaire
- Practical work results
- Validation of objectives
- Satisfaction survey :
- At the end of training: assessment form completed by the trainee
- At 3 months: evaluation form completed by the trainee after application to the company
- Certificate :
- Training certificate with assessment of learning provided to trainee
- Certificate of completion provided to employer
Teaching Methods
- Inter-company online training :
- Fast Internet connection, webcam, headset
- Presentation by Webex by Cisco
- Provision of course material in PDF format
- Labs on individual Cloud PC by RealVNC
- Intra-company face-to-face training on customer site : (details to be confirmed prior to training)
- Suggested supply by the customer :
- Training room
- Video projector
- Whiteboard
- Individual PC with AMD tools
- Provided by MVD Training :
- Course material in PDF format
- Practical work on individual PCs (loan of equipment available on request)
Recommended computer hardware
- Inter-company online training :
- Recent computer OS Linux or Windows 64-bits
- Fast Internet, webcam, headset
- Software tool WebEx Cisco
- AMD remote tools :
- Software tool RealVNC Viewer
- AMD local tools :
- Software tool AMD Vivado 2022.2
- Face-to-face training on customer site :
- Recent computer OS Linux or Windows 64-bits
- Software tool AMD Vivado 2022.2
Teaching staff
- William Duluc, Electronics and Telecoms Engineer, AMD Expert since 2009 and AMD Trainer since 2017 :
- Expert AMD FPGA - Language VHDL/Verilog - RTL Design
- Expert AMD SoC & MPSoC - Language C/C++ - System Design
- Expert DSP & AMD RFSoC – HLS - Matlab - Design DSP RF
- Expert AMD Versal – AI Engines – Heteregenous System Architect
Certified Partner
Notes
- Release date: 15/11/2024