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    • Adaptive Versal™
      • Versal™ Architecture, NoC and methodology
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    • Vitis™
      • Software design of embedded systems with the Vitis tool
      • Accelerating Applications with the Vitis
      • High-Level Synthesis with the Vitis HLS Tool
    • Adaptive SoCs
      • Embedded design for AMD SoCs
      • MPSoC Zynq™ UltraScale+
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    • Vivado™ & FPGA
      • AMD Vivado™
      • FPGA Architectures
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    • Digital Signal Processing on RFSoC and FPGA
      • Design with the Zynq™ UltraScale+ RFSoC
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      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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PLANNING

Check out our training schedule

Up coming training sessions

Designing an Integrated PCI Express System

September 29-30[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

Designing FPGAs Using the Vivado™

October 27-30[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

Accelerating Applications with the Vitis™ Unified Environment Software

November 12-14[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components

November 24-27[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

Adaptive Versal™

Adaptive Versal™

Versal™ Adaptive SoC

+
Vitis™

Vitis™

Vitis™, Vitis HLS

+
Adaptive SoC

Adaptive SoC

Zynq™, Zynq™ MPSoC, PetaLinux

+
VIVADO FPGA

Vivado™ & FPGA

Vivado™, UltraScale™, 7-Serie™,...

+
DSP

RFSoC & DSP

Digital Signal Processing on Zynq™ RFSoC and FPGA

+
HDL language

HDL language

Hardware Description Language

+

INTRA TRAINING on demand

ACCESS TIME: 2 MONTHS
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CERTIFICATE

QUALIOPI

CUSTOMER SATISFACTION

SATISFACTION

2024 : 94.7%

(115 Attendees)

2023 : 91.8%

(97 Attendees)

2022 : 94.1%

(172 Attendees)
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